By Bernd Höfflinger
The unlock of this moment quantity of CHIPS 2020 coincides with the fiftieth anniversary of Moore’s legislations, a serious 12 months marked by means of the tip of the nanometer roadmap and by means of a considerably lowered annual upward thrust in chip functionality. even as, we're witnessing an information explosion within the web, that's eating forty% extra electrical energy each year, resulting in fears of a huge blackout of the web via 2020.
The messages of the 1st CHIPS 2020, released in 2012, involved the belief of quantum steps for making improvements to the strength potency of all chip capabilities. With this moment quantity, we evaluate those messages and enlarge upon the main promising instructions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, mind- and human-vision-inspired processing, and effort harvesting for chip autonomy. The crew of authors, enlarged by way of extra global leaders in low-power, monolithic 3D, video, and Silicon brains, provides new vistas in nanoelectronics, promising Moore-like exponential progress sustainable via to the 2030s.
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Extra info for CHIPS 2020 VOL. 2: New Vistas in Nanoelectronics
II 59(2), 898–902 (2012) 18. : A 530 mV 10-lane SIMD processor with variation-resiliency in 45 nm SOI. In: 2012 IEEE International Solid-State Circuits Conference (ISSCC), Digestive Technology Papers, pp. 492–493, Feb 2012 19. 1, pp. 10–14, Feb 2014 20. : The Cross-Coupled Pair, Part I, Solid-State Circuits Magazine. Part II, Solid-State Circuits Magazine, Fall 2014, pp. 2–12 (2014) 21. : Exascale Computing—Fact or Fiction? SSCS Webinar (2014) Chapter 2 The Future of Low-Power Electronics Toshiaki Masuhara Abstract The number of integrated transistors has increased so rapidly that it has become evident that a further increase of the performance is limited by the power dissipation.
1 FD-SOI CMOS offers the best low-voltage sub-threshold transistor performance and minimal transistor- and circuit capacitances for optimal energy efﬁciency Technology Voltage range VDD (V) Max. VDD (MHz) Total power (mW) Peak efﬁciency pJ/operation Frequency/pJ (MHz/pJ) at min. 1), this 28 nm SOI design, compared with a 32 nm bulk and a 22 nm FinFET (Trigate) has an efﬁciency almost 3-times better than bulk CMOS and a frequency at minimum voltage 100-times and 30-times better, respectively. 5 3D CMOS Technologies The three-dimensional (3D) integration of transistors tackles the performance, the functional density, the interconnect capacitances and the process complexity of advanced CMOS circuits.
In memory-cell circuits, such as DRAM, SRAM, or Flash memories, electronic charge, the product of CV, where C is the capacity of the memory-node and V is the memory voltage, is used as means to store “1’s” and “0’s”. When the capacity C or the voltage V becomes small, the memory-signal becomes small. As a result, marginal sensing of the small signal becomes a problem. Since these memory-cells are volatile, they lose memory information when the supply-voltage is turned OFF. It is, therefore, necessary to keep the power-supply ON, or re-load the memory data, when the memory turns ON again.