By Manoj Sachdev
Disorder orientated trying out is predicted to play an important position in coming generations of expertise. Smaller characteristic sizes and bigger die sizes will make ICs extra delicate to defects that cannot be modeled by way of conventional fault modeling methods. moreover, with elevated point of integration, an IC may perhaps comprise assorted construction blocks. Such blocks comprise, electronic good judgment, PLAs, unstable and non-volatile thoughts, and analog interfaces. For such assorted construction blocks, conventional fault modeling and try out methods will develop into more and more insufficient. disorder orientated trying out equipment have come a ways from an insignificant fascinating educational workout to a troublesome commercial fact. Many elements have contributed to its business reputation. conventional ways of trying out glossy built-in circuits (ICs) were came across to be insufficient by way of caliber and economics of attempt. In a globally aggressive semiconductor industry position, total product caliber and economics became extremely important goals. In addition, digital structures have gotten more and more complicated and call for parts of optimum attainable caliber. checking out, regularly and, disorder orientated trying out, particularly, assist in figuring out those pursuits. illness orientated checking out for CMOS Analog and electronic Circuits is the 1st booklet to supply an entire assessment of the topic. it really is crucial examining for all layout and attempt pros in addition to researchers and scholars operating within the box. `A energy of this publication is its breadth. forms of designs thought of contain analog and electronic circuits, programmable common sense arrays, and stories. Having a fault version doesn't immediately supply a try. occasionally, layout for testability is important. Many layout for testability principles, supported via experimental proof, are included.' ... from the Foreword by means of Vishwani D. Agrawal
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Additional resources for Defect Oriented Testing for CMOS Analog and Digital Circuits
Testing of semiconductor RAMs is a typical example of functional level fault modeling. However, RAM fault modeling, test algorithm development, and testing is a mature discipline by itself. A lot of attention has been paid on 40 Digital CMOS Fault Modeling and Inductive Fault Analysis modeling [16,33,69] and testing of faults in RAM [57,72,74,85,87]. In Chapter 5 we address the defects and their detection strategies for RAMs. Hence, in this sub-section, we only address the function level fault modeling taking RAMs as a vehicle.
Some SOP faults in static CMOS logic gates require only one test vector, T2. If there is only one path from output to VSS (VDD) and the SOP fault affects this path, it is not possible to set the output to VSS (VDD). For example, in the case of a 2-input NAND gate (Fig. 4), test vector T2 (A=l, B=l) will detect SOP faults in the n-channel transistors. , ,, , ,, , ,, ,, VSS , I C1 C2 T1=TN* 1, 1 PFET in the T2=TP 1, 0 original gate T3=TP 0, 0 .... _---_ .... __ ...... T1=TP 0, 0 NFET in the T2=TN 1, 0 original gate T3=TN 1, 1 ..................
In the case of larger circuits having non-reconverging fanouts, the application of foregoing analysis is rather straight forward. However, in the case of reconverging fanouts, the reconverging branch may interfere with the propagation of the fault to a primary output. Gounden and Hayes  further simplified the fault class identification problem for certain cases. They introduced the concepts of intrinsic and extrinsic fault equivalence. These concepts were utilized to derive some general conditions for fault equivalence and non-equivalence for a given network topology.