Download FPGA-based Digital Convolution for Wireless Applications by Lei Guan PDF

By Lei Guan

This ebook provides crucial views on electronic convolutions in instant communications structures and illustrates their corresponding effective real-time field-programmable gate array (FPGA) implementations.

FPGAs or wide-spread all programmable units will quickly turn into common, serving because the “brains” of every kind of real-time shrewdpermanent sign processing platforms, like shrewdpermanent networks, clever houses and shrewdpermanent towns. The e-book examines electronic convolution by means of bringing jointly the next major components: the basic idea in the back of the mathematical formulae including corresponding actual phenomena; virtualized set of rules simulation including benchmark real-time FPGA implementations; and targeted, cutting-edge case reviews on instant functions, together with renowned linear convolution in electronic entrance ends (DFEs); nonlinear convolution in electronic pre-distortion (DPD) enabled high-efficiency instant RF transceivers; and speedy linear convolution in great multiple-input multiple-output (MIMO) systems.

After interpreting this publication, scholars and execs may be capable to:

· comprehend electronic convolution with inside-out details: detect what convolution is, why it can be crucial and the way it works.

· increase their FPGA layout talents, i.e., increase their FPGA-related prototyping strength with model-based hands-on examples.

· quickly extend their electronic sign processing (DSP) blocks: to envision the best way to quickly and successfully create (DSP) useful blocks on a programmable FPGA chip as a reusable highbrow estate (IP) core.

· improve their services as either “thinkers” and “doers”: minimize/close the distance among mathematical equations and FPGA implementations for current and rising instant applications.

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FPGA-based Digital Convolution for Wireless Applications

This e-book provides crucial views on electronic convolutions in instant communications platforms and illustrates their corresponding effective real-time field-programmable gate array (FPGA) implementations. FPGAs or familiar all programmable units will quickly develop into frequent, serving because the “brains” of every kind of real-time shrewdpermanent sign processing platforms, like clever networks, shrewdpermanent houses and shrewdpermanent towns.

Additional resources for FPGA-based Digital Convolution for Wireless Applications

Sample text

2 Linear Convolution Basics Fig. 1 Time Domain Perspective From time domain point view, linear convolution describes a processing how to derive the system output by given inputs and system impulse response. Specifically, the system output is the aggregation of the weighted input samples and its neighbour weighted samples in the time domain. Mathematically, linear convolution can be represented as below, yðnÞ ¼ xðnÞ Ã hðnÞ ¼ 1 X xðmÞhðn À mÞ ¼ m¼À1 1 X hðmÞxðn À mÞ ð3:5Þ m¼À1 In the definition, the impulse response h(n) is infinite in the time domain for generalization case, however in the most of the practical and stable digital signal processing systems, the impulse response is finite.

Based on Xilinx recommendations and our FPGA-based DSP design experience since 2006, System Generator can be quite helpful at the R&D prototyping stage for many scenarios. At early R&D stage of a brand new product, your algorithms are under developing so you may want to explore the algorithms regarding its system-level performance and corresponding complexity but without translating those “half-finished” algorithms into real hardware. Or at the prototyping stage for adding in new features on top of the existing products, you only need to design an add-on DSP function as part of the existing whole system design, however you have physical resource constraints so you may want to evaluate the new add-on DSP function first regarding its complexity with regards to the available physical resources left.

In this example, TP1 shows the original input data samples. TP2 represents 1 unit-delayed version of TP1. Similarly, TP3 is 1 cycle delayed version TP2. TP4 and TP5 show the outputs of the first and the second multipliers, respectively. TP6 illustrates the output of the first adder, which performs the addition operation between TP4 and TP5. Without any difficulty, we can recognize that the processing latency of the addition-chain-based fully-parallel architecture largely depends on how many adders are actually required.

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